The RENEW platform comprises servers, hubs, multiple Faros massive MIMO base stations, and clients. Each Faros consists of one hub and multiple radio heads. Each radio head comprises an IrisⓇ daisy chain of up to ten Iris modules. Each client is made of one Iris module. As such, Iris modules are the building blocks of both Faros base stations and clients.
Each Iris module is a custom programmable SDR device. It is designed and commercialized by the company Skylark WirelessⓇ which is a Rice University spinoff company. An Iris module comprises an SoC processor, a transceiver, a plug-and-play adaptor, an RF front-end, interconnects, peripherals, and an Ethernet port.
Each Iris module includes a SoC processor - a Xilinx Zynq 7z030 SoC processing unit. The outstanding technical specifications are
Each Iris module includes a transceiver - an LMS7002M software-defined transceiver chip from Lime Microsystems. The outstanding technical specifications for LMS7002M are
The FPGA fabric on the SoC processor is connected to the transceiver through high-speed lines to send and receive digital baseband samples. The SoC processor controls the transceiver through a SPI bus for various control settings such as frequency, gains, sample rate, etc. As of the writing of this document, streaming a maximum sample rate of 40 MHz is supported on Iris.
Each Iris module incorporates an RF front-end module through a standardized plug-and-play adaptor. Three types of commercially available front-end modules can be used on an Iris: DEV, dual-band BRS/CBRS, and UHF front-ends. They can be purchased on Skylark Wireless. A dual-band 2.5/3.6 GHz BRS/CBRS antenna with dual polarized feeds is also available for the Faros massive MIMO base station.
The plug-and-play adaptor documents are in
The dual-band BRS/CBRS antenna documents are in
RF front-end PCB documents are in https://github.com/skylarkwireless/sklk-hw/tree/master/Iris-FE-01-DEV.
An Iris with a DEV front-end is shown as below. The DEV front-end does not include amplifiers or filters. It simply forwards the transceiver’s output to RF antennas. The BRS/CBRS front-end works on the 2.5/3.5 GHz bands while the UHF front-end works on the 470 - 700 MHz bands.
Width of the module is 1.55”
Each Iris module in the daisy-chain receives a reference clock from its upstream interconnect, performs jitter-cleaning through its clock buffer, and then forwards it to its downstream interconnect. The upstream interconnect of the next Iris module shall be connected to the downstream interconnect of the previous Iris module. With this design, the entire Iris array remains phase-locked for coherent MIMO operation.
FPGA GPIO lines are also passed through the interconnects. Through these GPIO lines, a time synchronization mechanism is built into the FPGAs where each board can synchronously set its time reference with the rest of the Iris chain.
The GTX transceivers in FPGAs can distribute data to each Iris FPGA on the Iris chain through the interconnects with a maximum speed of 12.8 Gbps.
The entire chain is powered through the 48V power rail through the interconnects.
An Iris module is an Ethernet/IP-enabled device. This means communicating with Iris happens through a PC’s Ethernet port. Each Iris has an RJ45 Ethernet port. However, this port is only useful when no hub is available. This port can then be used to connect to a PC. This port can sustain a maximum rate of 1 Gbps which limits the sample rate that can be streamed to a PC.
In an Iris chain, only one Iris needs to be connected. The entire chain will be connected, automatically.
In case of a hub, all traffic from and to the Iris chain is routed to and from the hub as ethernet frames. The hub in turn will be connected through its backhaul ethernet ports (up to four 10 Gbps links) to any processing server.
Up to 10 Iris modules can be daisy-chained to form a coherent antenna array. An example of an Iris chain with 9 Iris modules is shown as below. An individual Iris is also shown on the right side of the Iris chain.
The individual Iris is powered by PoE whereas the Iris chain is powered through a breakout board to its left side.
Precise time synchronization is essential in a massive MIMO system and in beamforming in particular. The Faros base station has implemented a native time synchronization mechanism for this purpose. When time is synchronized, all Irise modules in the Faros system will have a synchronized time reference. This ensures the synchronized transmission and reception of signals OTA using a shared time value.
Time synchronization in the Faros system becomes slightly more complicated because of the daisy-chain architecture since sending a trigger (time sync) message to all Irise modules does not reach them at the same time, but rather has to go through each Iris to get to the next. So the time reference of each Iris module will have a delay with respect to its upstream Iris module. Therefore, a correction procedure is needed so that this delay is measured and calibrated out at the time of the trigger signal. This procedure is called “sync delays” as shown below. It is done before sending a trigger signal to all Iris modules for a synchronized transmission or reception.
Both sync delays and trigger signal are issued from the host software.
The sync delays procedure is explained as below.
Up to 8 Iris modules can be daisy-chained and packaged in an enclosure to form a remote radio head (RRH). At the head of the Iris chain, there is an SFP board which breaks out the data lines from the chain to the next SFP board.
This way multiple RHs can be daisy-chained together. Up to 6 RHs can be directly connected through fiber links to a central hub module. The hub provides data connectivity, clock reference, and time synchronization all through the same fiber links to all RHs, thereby making the entire system phase-coherent.
Below shows a rendering of the entire massive MIMO base station with multiple RHs connected to the central hub module (right side). The left side image shows the inside of an RH where four Irises are daisy-chained together.
Stack of Radio Head (RH) 1.5U form factor
Note that this configuration for 2.5 GHz operation where a half-wavelength antenna spacing for this band is observed. Since each Iris has a width equal to the half-wavelength in 3.5 GHz band, 8 Irises can be packaged in one RH resulting in 16 antennas per RH.
For both BRS and CBRS configurations, antennas are included inside the RH. There is a dual-polarized patch antenna installed per Iris in the RH.
The instructions in this section are for users with local access to the base stations and Iris modules, not for POWDER users. POWDER users do not need to update any images for any of their experiments. The RENEW team shall maintain the FARS system and iris clients in the POWDER network and shall keep their image up-to-date.
An Iris module requires a valid SD card to function. The SD card contains an FPGA image (
BOOT.BIN) and a linux kernel file (
Once powered on, a RED LED and a GREEN LED next to the RJ45 port will turn on. If a valid SD card presents on the Iris module, the RED LED will turn off after one second and the GREEN LED will stay on. This is an indication that the FPGA has been successfully loaded and the Iris module has been booted up.
An Iris module can use any type of micro SD cards with 8 GB or more. To upload the tar image file, use a micro SD card reader to attach the micro SD card to PC and then use the SD card flash tool “Soapy” to flash the micro SD card with the downloaded tar image. Use below command to flash the micro SD card:
sudo ./flash_sd_card -t /path/to/image.tar.gz
Similarly, the Faros hub needs to be updated with its tar image to its SD card in the same way.